The present invention relates to a method of forming a metal line of a semiconductor device, and more particularly, to a method of forming a metal line of a semiconductor device which uses a dual damascene process.
In fabricating various semiconductor devices, metal lines are generally formed to be subsequently used as electrically connect elements or lines, and contact plugs are generally formed to be subsequently used as vias or as a means for connecting lower metal lines and upper metal lines to each other.
As the semiconductor device becomes more highly integrated, the aspect ratio of a contact hole gradually increases. As a result, a difficulty has arisen in finding a suitable fabrication process for forming these highly resolved metal lines and their corresponding contact plugs or vias.
Materials for the metal line of a semiconductor device typically include aluminum (Al) and tungsten (W). These materials have been used mainly due to their good electrical conductivity properties. Recently, much interest has been directed towards the use of copper (Cu) as a next-generation material for a metal line. Copper exhibits an excellent electrical conductivity along with a corresponding low resistance as compared to using aluminum and tungsten. Therefore using copper can contribute to solving the problems associated with an RC signal delay in the semiconductor devices that are highly integrated and operate at an extremely high speed.
However, copper cannot be easily dry-etched into a wiring pattern. As such, in order to form a metal line using copper, a damascene process is employed. In the damascene process, a metal line is formed by first etching an insulation layer to define a metal line forming region. After completion of the metal line forming region, the metal line forming region is then filed with a copper layer.
The metal line forming region is either formed using a single damascene process or a dual damascene process. When using the dual damascene process, an upper metal line and a contact plug for connecting the upper metal line to a lower metal line can be simultaneously formed. Because the unwanted surface undulations produced due to the presence of the metal line can be removed, a subsequent process can be conveniently conducted when using the dual damascene process.
In the case of using the dual damascene process according to the conventional art, after primarily etching an insulation layer to define a contact hole, a metal line forming region is delimited on the insulation layer including the contact hole using a BARC (bottom anti-reflection coating) layer and a photoresist. A secondary etching then forms a trench which defines where a metal line will be defined in the insulation layer. Finally, a metal is overlain into the trench to subsequently form the metal line which includes the contact plug.
However, in the conventional dual damascene process, as shown in FIG. 1, an oxide residue 130 is likely to remain on the sidewalls of the trench in which the metal line is to be formed. Due to the presence of the oxide residue 130, a defect can be caused in a subsequent process.
In FIG. 1, the reference numeral 100 designates a semiconductor substrate, 110 designates a lower metal line, 120 designates an insulation layer, H designates a contact hole, and T designates a trench.
This defect brought about by the oxide residue 130 can be overcome by conducting the secondary etching as over-etching. However, in this case, because a top attack occurs on the lower metal line, it is difficult to secure an optimum process condition using the standard dual damascene techniques.